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preliminary taxi? compatible hotlink? transceiver CY7C9689 cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 may 4, 1999 features ? second-generation hotlink? technology amd? am7968/7969 taxichip? compatible 8-bit 4b/5b or 10-bit 5b/6b nrzi encoded data transport 10-bit or 12-bit nrzi pre-encoded (bypass) data transport synchronous ttl parallel interface embedded/bypassable 256 character transmit and receive fifos 50-to-200 mbaud serial signaling rate internal plls with no external pll components dual differential pecl-compatible serial inputs and outputs compatible with fiber-optic modules and copper cables built-in self-test (bist) for link testing link quality indicator single +5.0v 10%supply 100-pin tqfp functional description the CY7C9689 hotlink transceiver is a point-to-point com- munications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced, and unbal- anced copper transmission lines) at speeds ranging between 50 and 200 mbaud. the transmit section accepts parallel data of selectable widths and converts it to serial data, while the receiver section accepts serial data and converts it to parallel data of selectable widths. figure 1 illustrates typical connec- tions between two independent host systems and correspond- ing CY7C9689 parts. the CY7C9689 provides enhanced technology, increased functionality, a higher level of integra- tion, higher data rates, and lower power dissipation over the amd am7968/7969 taxichip products. the transmit section of the CY7C9689 hotlink can be con- figured to accept either 8- or 10-bit data characters on each clock cycle, and stores the parallel data into an internal syn- chronous transmit fifo. data is read from the transmit fifo and is encoded using embedded 4b/5b or 5b/6b encoders to improve its serial transmission characteristics. these encoded characters are then serialized, converted to nrzi, and output from two pecl compatible differential transmission line driv- ers at a bit-rate of either 10 or 20 times the input reference clock in 8-bit (or 10-bit bypass) mode, or 12 or 24 times the reference clock in 10-bit (or 12-bit bypass) mode. the receive section of the CY7C9689 hotlink accepts a se- rial bit-stream from one of two pecl compatible differential line receivers and, using a completely integrated pll clock synchronizer, recovers the timing information necessary for data reconstruction. the recovered bit stream is converted from nrzi to nrz, deserialized, framed into characters, 4b/5b or 5b/6b decoded, and checked for transmission errors. the recovered 8- or 10-bit decoded characters are then written to an internal receive fifo, and presented to the destination host system. the integrated 4b/5b and 5b/6b encoder/decoder may be by- passed (disabled) for systems that present externally encoded or scrambled data at the parallel interface. with the encoder bypassed, the pre-encoded parallel data stream is converted to and from a serial nrzi stream. the embedded fifos may also be bypassed (disabled) to create a reference-locked seri- al transmission link. for those systems requiring even greater fifo storage capability, external fifos may be directly cou- pled to the CY7C9689 through the parallel interface without the need for additional glue-logic. the ttl parallel i/o interface may be configured as either a fifo (configurable for depth expansion through external fifos) or as a pipeline register extender. the fifo configura- tions are optimized for transport of time-independent (asyn- chronous) 8- or 10-bit character-oriented data across a link. a built-in self-test (bist) pattern generator and checker allows for testing of the high-speed serial data paths in both the trans- mit and receive sections, and across the interconnecting links. hotlink devices are ideal for a variety of applications where parallel interfaces can be replaced with high-speed, point-to- point serial links. some applications include interconnecting workstations, backplanes, servers, mass storage, and video transmission equipment. figure 1. hotlink system connections deserializer framer receive fifo tr a n s m i t fifo serializer CY7C9689 receive data transmit data system host control status deserializer framer 4b/5b, 5b/6b decoder receive fifo transmit fifo 4b/5b, 5b/6b encoder serializer CY7C9689 receive data tran smi t data system host control status serial link serial link 4b/5b, 5b/6b encoder 4b/5b, 5b/6b decoder
preliminary CY7C9689 2 txcmd[1:0] txhalt txhalf txfull txempty rangesel refclk spdsel ce rxhalf rxen rxfull rxempty rxclk rxsc/d vltn rxcmd[1:0] rxdata[7:0] rxdata[9:8]/rxcmd[2:3] rxrst extfifo byte8/10 fifobyp encbyp operating receive fifo rx rx pll tx pll tx transmit fifo chip enable link deserializer outa outb a/b ina inb rfen rxbisten txbisten 256 byte mode control framer decoders 4b/5b, 5b/6b quality control control 256 byte txclk cardet txdata[9:8]/txcmd[2:3] txdata[7:0] txrst txen txsc/d rxmode[1:0] dlb curseta cursetb CY7C9689 hotlink logic block diagram encoders 4b/5b, 5b/6b serializer lfi reset test
preliminary CY7C9689 3 pin configuration 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 spdsel rangesel rfen txfull ce txhalf rxsc/d txclk v ss v ss v dd rxdata[1] txcmd[1] rxrst rxen rxdata[0] txempty v ss txcmd[0] v dd txdata[9]/txcmd[2] rxdata[2] v ss reset v dd 58 57 56 55 54 53 52 51 test a/b lfi v ss dlb vltn v ss rxclk rxfull v ss v dd v dd txen txhalt txbisten v ss txrst rxhalf txsc/d rxempty txdata[0] rxcmd[1] rxmode[1] rxmode[0] refclk 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 cardet v ssa v dda curseta v dda v dda outa ? ina ? v ssa v dda v dda v ssa v ssa v ssa ina+ inb+ inb ? outb ? outb+ v dda v ssa cursetb rxbisten v ssa outa+ 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 byte8/10 extfifo rxdata[3] rxdata[4] txdata[8]/txcmd[3] rxdata[5] txdata[5] rxdata[6] rxdata[7] v ss v ss txdata[3] rxdata[8/rxcmd[3]] txdata[6] txdata[7] txdata[4] v dd txdata[2] rxdata[9]/rxcmd[2] txdata[1] rxcmd[0] fifobyp encbyp v ss v ss 33 32 31 30 29 28 27 26 CY7C9689
preliminary CY7C9689 4 ( pin descriptions pin name i/o characteristics signal description transmit path signals 68 txclk ttl clock input transmit fifo clock. used to sample all transmit fifo and related interface signals. 44, 42, 40, 36, 34, 32, 30, 22 txdata[7:0] ttl input, sampled on txclk or refclk parallel transmit data input. when selected (ce =low and txen = asserted), information on these inputs is processed as data when txsc/d is low and ignored otherwise. when the encoder is bypassed (encbyp is low), txdata[7:0] functions as the least significant eight bits of the 10- or 12-bit pre-encoded transmit character. when the transmit fifo is enabled (fifobyp is high), these inputs are sam- pled on the rising edge of txclk. when the transmit fifo is bypassed (fifobyp is low) these inputs are captured on the rising edge of refclk. 54, 46 txdata[9:8]/ txcmd[2:3] ttl input, sampled on txclk or refclk parallel transmit data or command input. when selected, byte8/10 is high, and the encoder is enabled (encbyp is high), information on these inputs are processed as txcmd[2:3] if txsc/d is high and ignored otherwise. when selected, byte8/10 is low, and the encoder is enabled (encbyp is high), information on these inputs are processed as txdata[9:8] if txsc/d is low and ignored otherwise. when the encoder is bypassed (encbyp is low), txdata[9:8] functions as the 9th and 10th bits of the 10- or 12-bit pre-encoded transmit character. when the transmit fifo is enabled (fifobyp is high), these inputs are sam- pled on the rising edge of txclk. when the transmit fifo is bypassed (fifobyp is low), these inputs are captured on the rising edge of refclk. 58, 56 txcmd[1:0] ttl input, sampled on txclk or refclk parallel transmit command input. when selected and the encoder is enabled (encbyp is high), information on these inputs is processed as a command when txsc/d is high and ignored otherwise. when byte8/10 is high and the encoder is bypassed (encbyp is low), the txcmd[1:0] inputs are ignored. when byte8/10 is low and when the encoder is bypassed (encbyp is low), the txcmd[1:0] inputs function as the 11th and 12th (msb) bits of the 12-bit pre-encoded transmit character. when the transmit fifo is enabled (fifobyp is high), these inputs are sam- pled on the rising edge of txclk. when the transmit fifo is bypassed (fifobyp is low), these inputs are sampled on the rising edge of refclk. 20 txsc/d ttl input, sampled on txclk or refclk command or data input selector. when selected, byte8/10 is high, and the encoder is enabled (encbyp is high), this input selects if the data or command inputs are processed. if txsc/d is high, the value on txcmd[3:0] is captured as one of sixteen pos- sible commands, and the data on the txdata[7:0] bits are ignored. if txsc/d is low, the information on txdata[7:0] is captured as one of 256 possible 8- bit data values, and the information on the txcmd[3:0] bus is ignored. when byte8/10 is low and the encoder is enabled (encbyp is high) this input selects if the data or command inputs are processed. if txsc/d is high, the information on txcmd[1:0] is captured as one of four possible com- mands, and the information on the txdata[9:0] bits are ignored. if txsc/d is low, the information on txdata[9:0] is captured as one of 1024 possible 10- bit data values, and the information on the txcmd[1:0] bus is ignored. when the encoder is bypassed (encbyp is low) txsc/d is ignored
preliminary CY7C9689 5 18 txen ttl input, sampled on txclk or refclk transmit enable. txen is sampled on the rising edge of the txclk or refclk input and enables parallel data bus write operations (when selected). the device is selected when txen is asserted during a clock cycle immediately following one in which ce is sampled low. depending on the level on extfifo, the asserted state for txen can be active high or active low. if extfifo is low, then txen is active low and data is captured on the same clock cycle where txen is sampled low. if extfifo is high, then txen is active high and data is captured on the clock cycle following any clock edge when txen is sampled high. 7 txbisten ttl input, asynchronous transmitter bist enable. when txbisten is low, the transmitter generates a 511-character repeating sequence, that can be used to validate link integrity. this 4b/5b bist sequence is generated regardless of the state of other configuration inputs. the transmit- ter returns to normal operation when txbisten is high. all transmit fifo read operations are suspended when bist is active. 16 txrst ttl input, sampled on txclk reset transmit fifo. when the transmit fifo is enabled (fifobyp is high), txen is deasserted, ce is asserted (low), and txrst is sampled low by txclk for seven cycles, the transmit fifo begins its internal reset process. the transmit fifo txfull flag is asserted and the host interface counter and address pointer are zeroed. this reset propagates to the serial transmit side, any remaining counters and pointers. the txfull flag is asserted until both sides of the transmit fifo have reset. while txrst remains asserted, the transmit fifo remains in reset and the txfull output remains asserted. when the transmit fifo is bypassed (fifobyp is low), txrst is ignored. 9 txhalt ttl input, sampled on txclk transmitter halt control input. when txhalt is asserted low, transmission of data is suspended and the hotlink taxi transmits sync characters. when txhalt is deasserted high, normal data processing proceeds. if the transmit fifo is enabled (fifobyp is high), the interface is allowed to continue loading data into the transmit fifo while txhalt is asserted. 72 txfull three-state ttl out- put, changes following txclk or refclk transmit fifo full status flag. when the transmit fifo is enabled (fifobyp is high) and its flags are driven (ce is low), txfull is asserted when four or fewer characters can be written to the hotlink transmit fifo. if a transmit fifo reset has been initiated (txrst was sampled asserted for a minimum of seven txclk cycles), txfull is asserted to enforce the full/unavailable status of the transmit fifo during reset. when the transmit fifo is bypassed (fifobyp is low), the txfull output changes after the rising edge of refclk. txfull is asserted when the trans- mitter is busy (not accepting a new data or command characters) and deas- serted when new characters can be accepted. when the transmit fifo is bypassed and rangesel is high or spdsel is low, txfull toggles at the character rate to provide a character rate reference control-indication since refclk is operating at twice of the data rate. the asserted state of this output (high or low) is determined by the state of the extfifo input. when extfifo is low, txfull is active low. when extfifo is high, txfull is active high. pin descriptions (continued) pin name i/o characteristics signal description
preliminary CY7C9689 6 70 txhalf three-state ttl out- put, changes following txclk transmit fifo half-full status flag. when the transmit fifo is enabled (fifobyp is high and ce is low) txhalf is asserted when the hotlink transmit fifo is half full (128 char- acters is half full). if a transmit fifo reset has been initiated (txrst was sampled asserted for a minimum of seven txclk cycles), txhalf is asserted to enforce the full/unavailable status of the transmit fifo during reset. when the transmit fifo is bypassed (fifobyp is low), txhalf remains deasserted, having no logical function. txhalf is forced to the high-z state only during a ? full-chip ? reset (i.e., while reset is low). 60 txempty three-state ttl out- put, changes following txclk or refclk transmit fifo empty status flag. when the transmit fifo is enabled (fifobyp is high and ce is low), txempty is asserted when the hotlink transmit fifo has no data to forward to the encoder. if a transmit fifo reset has been initiated (txrst was sampled asserted for a minimum of seven txclk cycles), txempty is deasserted and remains deasserted until the transmit fifo reset operation is complete. when the transmit fifo is bypassed (fifobyp is low), txempty is assert- ed to indicate that the transmitter can accept data. txempty is also used as a bist progress indicator when txbisten is asserted. when txbisten is asserted low, txempty becomes the transmit bist-loop counter indicator (regardless of the logic state of fifobyp ). in this mode txempty is asserted for one txclk or refclk period at the end of each transmitted bist sequence. note: during bist operations, when the transmit fifo is enabled (fifobyp is high), it is necessary to keep txclk operating, even though no data is loaded into the transmit fifo and txen is never asserted, to allow the txempty flag to respond to the bist state changes. the asserted state of this output (high or low) is determined by the state of the extfifo input. when extfifo is low, txempty is active low. when extfifo is high, txempty is active high. if ce is sampled asserted (low), txempty is driven to an active state. if ce is sampled deasserted (high), txempty is placed into a high-z state. receive path signals 8 rxclk bidirectional ttl clock receive clock. when the receive fifo is enabled (fifobyp is high), this clock is the receive interface input clock and is used to control receive fifo read and reset, oper- ations. when the receive fifo is bypassed (fifobyp is low), this clock becomes the recovered receive pll character clock output which runs contin- uously at the character rate. 41, 43, 45, 47, 48, 53, 59,61 rxdata[7:0] three-state ttl out- put, changes following rxclk parallel receive data outputs. when the decoder is enabled (encbyp is high), the low-order eight bits of the decoded data character are presented on the rxdata[7:0] outputs. command characters, when they are received, do not disturb these outputs. when the decoder is bypassed, the low order eight bits of the non-decoded character are presented on the rxdata[7:0] outputs. when the receive fifo is disabled (fifobyp is low), these outputs change on the rising edge of the rxclk output. when the receive fifo is enabled (fifobyp is high), these outputs change on the rising edge of rxclk input. rxen is the three-state control for rxdata[7:0]. pin descriptions (continued) pin name i/o characteristics signal description
preliminary CY7C9689 7 31, 33 rxdata[9:8]/ rxcmd[2:3] three-state ttl out- put, changes following rxclk parallel receive data or command output. when byte8/10 is high and the decoder is enabled (encbyp is high) these outputs reflects the value for the most recently received rxcmd[2:3]. when byte8/10 is low and the decoder is enabled (encbyp is high) these outputs reflects the value for the most recently received rxdata[9:8]. when the decoder is bypassed (encbyp is low), rxdata[9:8] functions as the 9th and 10th bits of the 10- or 12-bit non-decoded receive character. when the receive fifo is disabled (fifobyp is low), these outputs change on the rising edge of the rxclk output. when the receive fifo is enabled (fifobyp is high), these outputs change on the rising edge of the rxclk input. rxen is a three-state control for rxdata[9:8]/rxcmd[2:3]. 23, 29 rxcmd[1:0] three-state ttl out- put, changes following rxclk parallel receive command outputs. when the decoder is enabled (encbyp is high) these outputs reflect the value for the most recently received rxcmd[1:0]. when byte8/10 is high and the decoder is bypassed (encbyp is low), these outputs have no meaning and are driven low. when byte8/10 is low and the decoder is bypassed (encbyp is low), rxcmd[1:0] functions as the 11th and 12th (msb) bits of the 12-bit non- decoded receive character. when the receive fifo is disabled (fifobyp is low), this output changes on the rising edge of the rxclk output. when the receive fifo is enabled (fifobyp is high), these outputs change on the rising edge of the rxclk input. rxen is a three-state control for rxcmd[1:0]. 69 rxen ttl input, sampled on rxclk receive enable input. rxen is a three-state control for the parallel data bus read operations. rxen is sampled on the rising edge of the rxclk input (or output) and enables parallel data bus read operations (when selected). the device is selected when rxen is asserted during an rxclk cycle immediately following one in which ce is sampled low. the parallel data pins are driven to active levels after the rising edge of rxclk. when rxen is de-asserted (ending the selection) the parallel data pins are high-z after the rising edge of rxclk. depending on the level on extfifo, this signal can be active high or active low. if extfifo is low, then rxen is active low. if extfifo is high, then rxen is active high. data is delivered on the clock cycle following any clock edge when rxen is active. 65 rxsc/d three-state ttl out- put, changes following rxclk command or data output indicator. when byte8/10 is high and the decoder is enabled (encbyp is high), this output indicates which group of outputs have been updated. if rxsc/d is high, rxcmd[3:0] contains a new command. the data on the rxdata[7:0] pins remain unchanged. if rxsc/d is low, rxdata[7:0] contains a new data char- acter. the command output on rxcmd[3:0] remain unchanged. when byte8/10 is low and the decoder is enabled (encbyp is high), this output indicates which group of outputs have been updated. if rxsc/d is high, rxcmd[1:0] contains a new command and the data on the rxdata[9:0] remain unchanged. if rxsc/d is low, rxdata[9:0] contains a new data char- acter and the command output on rxcmd[1:0] remain unchanged. when the decoder is bypassed (encbyp is low) rxsc/d is not used and may be left unconnected. rxen is a three-state control for rxsc/d . pin descriptions (continued) pin name i/o characteristics signal description
preliminary CY7C9689 8 6 vltn three-state ttl out- put, changes following rxclk code rule violation detected. vltn is asserted in response to detection of a 4b/5b or 5b/6b character that does not meet the coding rules of these characters. when vltn is asserted, the values on the output data and command buses remain unchanged. vltn remains asserted for one rxclk period. vltn is used to report character mismatches when rxbisten is driven low. vltn is driven low when the decoder is bypassed (encbyp is low). rxen is a three-state control for vltn. 67 rxrst ttl input, sampled on rxclk receive fifo reset. active low. when the receive fifo is enabled (fifobyp is high), rxen is deasserted, ce is asserted (low), and rxrst is sampled while asserted (low) by rxclk for seven cycles, the receive fifo begins its internal reset process. once the reset operation is started, the rxempty flag is asserted and the interface counters and address pointer are zeroed. the reset operation pro- ceeds to clear out the internal write pointers and counters. the rxempty output remains asserted through the reset operation and remains asserted until new data is written to the receive fifo. while rxrst remains asserted, the receive fifo remains in reset and cannot accept received characters. when the receive fifo is bypassed (fifobyp is low), rxrst is ignored. 24, 25 rxmode[1:0] static control input ttl levels normally wired high or low receiver discard policy mode select. 00b ? allows all characters to be written into the receive fifo or output to the receive data bus 01b ? discards all jk or lm sync characters except the ? last ? one of a string of sync characters. single sync characters in a data stream are included in the data written into the receive fifo. 1xb ? discards all jk or lm sync characters. the data stream written into the receive fifo does not include sync characters. 77 rxbisten ttl input, asynchronous receiver bist enable. active low. when low, the receiver is configured to perform a character-for-character match of the incoming data stream with a 511-character bist sequence. the result of character mismatches are indicated on the vltn pin. completion of each 511-character bist loop is accompanied by an assertion pulse on the rxfull flag. the state of encbyp , fifobyp , and byte8/10 have no effect on bist operation. 73 rfen ttl input, asynchronous reframe enable. used to control when the framer is allowed to adjust the character boundaries based on detection of one or more framing characters in the data stream. when framing is enabled (rfen is high) the receive framer realigns the serial stream to the incoming 10-bit jk sync character (if byte8/10 is high) or the 12-bit lm sync character (if byte8/10 is low). framing is disabled when rfen is low. the deassertion of rfen freezes the character boundary relationship between the serial stream and character clock. rfen is an asynchronous input, sampled by the internal receive pll character clock. pin descriptions (continued) pin name i/o characteristics signal description
preliminary CY7C9689 9 10 rxfull three-state ttl out- put, changes following rxclk receive fifo full flag. when the receive fifo is enabled (fifobyp is high) and its flags are driven (ce is low), rxfull is asserted when space is available for four or fewer characters to be written to the hotlink receive fifo. if the rxclk input is not continuous or the fifo is accessed at a rate slower than data is being received, rxfull may also indicate that some data has been lost because of fifo overflow. when the receive fifo is bypassed (fifobyp is low), rxfull is deassert- ed to indicate that valid data may be present. rxfull is also used as a bist progress indicator, and pulses once every pass through the 511 character bist loop. when rxbisten is asserted (low), rxfull becomes the receive bist loop progress indicator (regardless of the logic state of fifobyp ). while rxbisten is asserted, rxfull is asserted until the receiver detects the start of the bist pattern. then rxfull is deasserted for the duration of the bist pattern, puls- ing asserted for one rxclk period on the last symbol of each bist loop. if 14 of 28 consecutive symbols are received in error, rxfull returns to the asserted state until the start of a bist pattern is again detected. the asserted state of this output (high or low) is determined by the state of the extfifo input. when extfifo is low, rxfull is active low. when extfifo is high, rxfull is active high. 19 rxhalf three-state ttl out- put, changes following rxclk receive fifo half-full flag. when the receive fifo is enabled (fifobyp is high and ce is low) rxhalf is asserted when the hotlink receive fifo is half full (128 char- acters is half full). if a receive fifo reset has been initiated (rxrst was sampled asserted for a minimum of seven rxclk cycles), rxhalf is deas- serted to enforce the empty/unavailable status of the receive fifo during reset. if fifobyp is low, rxhalf remains deasserted having no logical function. rxhalf is forced to the high-z state only during a ? full-chip ? reset (i.e., while reset is low). 21 rxempty three-state ttl out- put, changes following rxclk receive fifo empty flag. when the receive fifo is enabled (fifobyp is high) and its flags are driven (ce is low), rxempty is asserted when the hotlink receive fifo has no data to forward to the parallel interface. if a receive fifo reset has been initi- ated (rxrst was sampled asserted for a minimum of seven rxclk cycles), rxempty is asserted to enforce the empty/unavailable status of the receive fifo during reset. any read operation occurring when rxempty is asserted results in no change in the fifo status, and the data from the last valid read remains on the rxdata bus. when the receive fifo is bypassed but the decoder is enabled, rxempty is used as a valid data indicator. when deasserted it indicates that valid data is present at the rxdata or rxcmd outputs as indicated by rxsc/d . when asserted it indicates that a sync character (jk or lm) is present on the rxcmd output pins. when the receive fifo is bypassed (fifobyp is low), rxempty is deasserted whenever data is ready. the asserted state of this output (high or low) is determined by the state of the extfifo input. when extfifo is low, rxempty is active low. when extfifo is high, rxempty is active high. pin descriptions (continued) pin name i/o characteristics signal description
preliminary CY7C9689 10 control signals 71 ce ttl input sampled on txclk , rxclk , or refclk chip enable input. active low. when ce is asserted and sampled low by rxclk, the receive fifo status flags are driven to their active states. when this input is deasserted and sampled by rxclk, the receive fifo status flags are placed in a high-z state. when ce has been sampled low and rxen changes from deasserted to asserted and is sampled by rxclk, the rxsc/d , rxdata[7:0], rxdata[9:8]/ rxcmd[2:3] and vltn output drivers are enabled and go to their driven levels. these pins remain driven until rxen is sampled deasserted. when the transmit fifo is enabled (fifobyp is high), and ce is asserted and sampled by txclk, the transmit fifo status flags are driven to their active states. when this input is deasserted and sampled by txclk, the transmit fifo status flags are placed in a high-z state. when the transmit fifo is bypassed (fifobyp is low), and ce is asserted and sampled by refclk, the transmit fifo status flags are driven to their active states. when this input is deasserted and sampled by refclk, the transmit fifo status flags are placed in a high-z state. when the transmit fifo is enabled (fifobyp is high), ce has been sampled low, and txen changes from deasserted to asserted and is sampled by txclk, the txsc/d , txdata[7:0], txdata[9:8]/rxcmd[2:3], and txcmd[1:0] inputs are sampled and passed to the transmit fifo. these inputs are sampled on all consecutive txclk cycles until txen is sampled deasserted. when the transmit fifo is bypassed (fifobyp is low), ce has been sampled low, and txen changes from deasserted to asserted and is sampled by ref- clk, the txsc/d , txdata[7:0], txdata[9:8]/rxcmd[2:3], and txcmd[1:0] inputs are sampled and passed to the encoder or serializer as directed by other control inputs. these inputs are sampled on all consecutive refclk cycles until txen is sampled deasserted. 12 refclk ttl clock input pll frequency reference clock. this clock input is used as the timing reference for the transmit and receive plls. when the transmit fifo is bypassed (fifobyp is high), refclk is also used as the clock for the parallel transmit interface. 75 spdsel static control input ttl levels normally wired high or low speed select. used to select from one of two operating serial rates for the cy7b9689. when spdsel is high, the signaling rate is between 100 and 200 mbaud. when low, the signaling rate is between 50 and 100 mbaud. used in combination with rangesel and byte8/10 to configure the vco multipliers and dividers. 74 rangesel static control input ttl levels normally wired high or low range select. selects the proper prescaler for the refclk input. if rangesel is low, the refclk input is passed directly to the transmit pll clock multiplier. if rangesel is high, reflck is divided by two before being sent to the trans- mit pll multiplier. when the transmit fifo is bypassed (fifobyp is low), with rangesel high or spdsel low, txfull toggles at half the refclk rate to provide a character rate indication, and to show when data can be accepted. 51 reset asynchronous ttl input master reset for internal logic. pulsed low for one or more refclk cycles. pin descriptions (continued) pin name i/o characteristics signal description
preliminary CY7C9689 11 28 fifobyp static control input ttl levels normally wired high or low fifo bypass enable. when asserted, the transmit and receive fifos are bypassed. in this mode txclk is not used. instead all transmit data must be synchronous to refclk. transmit fifo status flags are synchronized to refclk. all received data is synchronous to rxclk output. receive fifo status flags are synchronized to rxclk (the recovered receive pll character clock). when not asserted, the transmit and receive fifos are enabled. in this mode all transmit fifo writes are synchronized to txclk, and all receive fifo reads are synchronous to the rxclk input. 50 byte8/10 static control input ttl levels normally wired high or low 8/10-bit parallel data size select. when set for 8-bit data (byte8/10 is high) and the encoder is enabled (encbyp is high), 8-bit data characters and 4-bit command characters are captured at the txdata[7:0] or txcmd[3:0] inputs (selected by the txsc/d input) and passed to the transmit fifo (if enabled) and encoder. received characters are decoded, passed through the receive fifo (if enabled) and presented at either the rxdata[7:0] or rxcmd[3:0] outputs and indicated by the rxsc/d output. when set for 8-bit data (byte8/10 is high) and the encoder is bypassed (encbyp is low), the internal data paths are set for 10-bit characters. each received character is presented to the receive fifo (if enabled) and is passed to the rxdata[9:0] outputs. when set for 10-bit data (byte8/10 is low) and the encoder is enabled (encbyp is high), 10-bit data characters and 2-bit command characters are captured at the txdata[9:0] or txcmd[1:0] inputs (selected by the txsc/d input) and passed to the transmit fifo (if enabled) and encoder. received characters are decoded, passed through the receive fifo (if enabled) and presented at either the rxdata[9:0] or rxcmd[1:0] outputs and indicated by the rxsc/d output. when set for 10-bit data (byte8/10 is low) and the encoder is bypassed (encbyp is low), the internal clock data paths are set for 12-bit characters. each received character is presented to the receive fifo (if enabled) and is passed to the rxdata[9:0] and the rxcmd[1:0] outputs. 49 extfifo static control input ttl levels normally wired high or low external fifo mode. extfifo modifies the active state of the rxen and txen inputs and the timing of the transmitter and receiver data buses. when configured for external fifos (extfifo is high), txen is assumed to be driven by the empty flag of an attached cy7c42x5 fifo, and rxen is assumed to be driven by the almost full flag of an attached cy7c42x5 fifo. in this mode the active data transition is in the clock following the clock edge that ? enables ? the data bus. when not configured for external fifos (extfifo is low), txen is assumed to be driven as a pipeline register and rxen is assumed to be driven by a controller for a pipeline register. in this mode the active data transition is within the same clock as the clock edge that ? enables ? the data bus. extfifo also modifies the output state of the receive and transmit fifo flags. when configured for external fifos (extfifo is high), the full and empty fifo flags are active high (the half full flag is always active low). when not configured for external fifos (extfifo is low), all of the fifo flags are active low. 27 encbyp static control input ttl levels normally wired high or low enable encoder bypass mode. when asserted, both the encoder and decoder are bypassed. data is transmit- ted without 4b/5b or 5b/6b encoding (but with nrzi encoding), lsb first. re- ceived data are presented as parallel characters to the parallel interface without decoding. when deasserted, data is passed through both the encoder in the transmit path and the decoder in the receive path. pin descriptions (continued) pin name i/o characteristics signal description
preliminary CY7C9689 12 analog i/o and control 89, 90, 81, 82 outa outb pecl compatible differential output differential serial data outputs. these pecl-compatible differential outputs are capable of driving terminated transmission lines or commercial fiberoptic transmitter modules. to minimize the power dissipation of unused outputs, the outputs should be left unconnected and the associated curseta or cursetb should be connected to v dd . 85, 86, 93, 94 ina inb pecl compatible differential input differential serial data inputs. these inputs accept the serial data stream for deserialization and decoding. only one serial stream at a time may be fed to the receive pll to extract the data content. this stream is selected using the a/b input. 97 curseta analog current-set resistor input for outa . a precision resistor is connected between this input and a clean ground to set the output differential amplitude and currents for the outa differential driver. 78 cursetb analog current-set resistor input for outb . a precision resistor is connected between this input and a clean ground to set the output differential amplitude and currents for the outb differential driver. 100 cardet pecl input, asynchronous carrier detect input. used to allow an external device to signify a valid signal is being presented to the high speed pecl input buffers, as is typical on an optical module. when cardet is deasserted low, the lfi indicator asserts low signifying a link fault. this input can be tied high for copper media applications. 2a/b asynchronous ttl input input a or input b selector. when high, input ina is selected, when low, inb is selected. 3lfi three-state ttl out- put, changes following rxclk link fault indication output. active low. lfi changes synchronous with rxclk. this output is driven low when the serial link currently selected by a/b is not suitable for data recovery. this could be because: 1. serial data amplitude is below acceptable levels 2. input transition density is not sufficient for pll clock recovery 3. input data stream is outside an acceptable frequency range of operation 4. cardet is low 5 dlb asynchronous ttl input diagnostic loop back selector. when dlb is low, loop mode is off. output of the transmitter shifter is routed to both outa and outb and the serial input selected by a/b is routed to the receive pll for data recovery. when dlb is high, diagnostic loopback is enabled. output of the transmitter serial data is routed to the receive pll for data recovery. primarily used for system diagnostic test. the serial inputs are ignored and outa and outb are both active. 1 test asynchronous ttl input normally wired high test mode select. used to force the part into a diagnostic test mode used for factory ate test. this input must be tied high during normal operation. power 80, 87, 88, 95, 96 v dda power for pecl compatible i/o signals and internal circuits. 76, 79, 83, 84, 91, 92, 99 v ssa ground for pecl compatible i/o signals and internal circuits. pin descriptions (continued) pin name i/o characteristics signal description
preliminary CY7C9689 13 14, 17, 35, 55, 62, 64 v dd power for ttl i/o signals and internal circuits. 4,11, 13, 15, 26, 37, 38, 39, 52, 57, 63, 66 v ss ground for ttl i/o signals and internal circuits. pin descriptions (continued) pin name i/o characteristics signal description table 1. transmit input bus signal map txdata bus input bit transmit encoder mode [1] encoded 8-bit character stream [2] pre-encoded 10-bit character stream encoded 10-bit character stream [3] pre-encoded 12-bit character stream txsc/d txsc/d txsc/d txdata[0] txdata[0] txd[0] [4] txdata[0] txd[0] [5] txdata[1] txdata[1] txd[1] txdata[1] txd[1] txdata[2] txdata[2] txd[2] txdata[2] txd[2] txdata[3] txdata[3] txd[3] txdata[3] txd[3] txdata[4] txdata[4] txd[4] txdata[4] txd[4] txdata[5] txdata[5] txd[5] txdata[5] txd[5] txdata[6] txdata[6] txd[6] txdata[6] txd[6] txdata[7] txdata[7] txd[7] txdata[7] txd[7] txdata[8]/txcmd[3] txcmd[3] txd[8] txdata[8] txd[8] txdata[9]/txcmd[2] txcmd[2] txd[9] txdata[9] [3] txd[9] txcmd[1] txcmd[1] txcmd[1] txd[10] [5] txcmd[0] txcmd[0] txcmd[0] txd[11] notes: 1. all open cells are ignored. 2. when encbyp is high and byte8/10 is high, transmitted bit order is the encoded form (msb to lsb) of txdata[7,6,5,4] and txdata[3,2,1,0] or txcmd[3,2,1,0] as selected by txsc/d. 3. when encbyp is high and byte8/10 is low, transmitted bit order is the encoded form (msb to lsb) of txdata[8,7,6,5,4] and txdata[9,3,2,1,0] or txcmd[1,0] as selected by txsc/d. 4. when encbyp is low and byte8/10 is high, the transmitted bit order is (lsb to msb) txd[0,1,2,3,4,5,6,7,8,9]. 5. when encbyp is low and byte8/10 is low, the transmitted bit order is (lsb to msb) txd[0,1,2,3,4,5,6,7,8,9,11,10].
preliminary CY7C9689 14 . CY7C9689 hotlink operation overview the CY7C9689 is designed to move parallel data across both short and long distances with minimal overhead or host sys- tem intervention. this is accomplished by converting the par- allel characters into a serial bit-stream, transmitting these se- rial bits at high speed, and converting the received serial bits back into the original parallel data format. the CY7C9689 offers a large feature set, allowing it to be used in a wide range of host systems. some of the of configuration options are amd taxichip 4b/5b & 5b/6b compatible encoder/decoder amd taxichip compatible serial link amd taxichip parallel command and data i/o bus architecture 8-bit or 10-bit character size user-definable data packet or frame structure two-octave data rate range asynchronous (fifoed) or synchronous data interface embedded or bypassable fifo data storage encoded or non-encoded multi-phy capability this flexibility allows the CY7C9689 to meet the data transport needs of almost any system. transmit data path transmit data interface/transmit data fifo the transmit data interface to the host system is configurable as either an asynchronous buffered (fifoed) parallel interface or as a synchronous pipeline register. the bus itself can be configured for operation with either 8-bit or 10-bit character widths. when configured for asynchronous operation (where the host- bus interface clock operates asynchronous to the serial char- acter and bit stream clocks), the host interface becomes that of a synchronous fifo clocked by txclk. in this configura- tion an internal 256 character transmit fifo is enabled that allows the host interface to be written at any rate from dc to 50 mhz. when configured for synchronous operation, the transmit in- terface is clocked by refclk and operates synchronous to the internal character and bit-stream clocks. the input register can be written at either 1/10th or 1/12th the serial bit rate. this interface can be clocked at up to 40 mhz when configured for 8-bit data width, and up to 33 mhz when configured for 10-bit data bus width. actual clock rate depends on data rate as well as rangesel and spdsel logic levels. both asynchronous and synchronous interface operations support user control over the logical sense of the fifo status flags. full and empty flags on both the transmitter and receiver can be active high or active low. this facilitates interfacing table 2. receiver output bus signal map rxdata bus output bit receiver decoder mode [1] encoded 8-bit character stream [7] pre-encoded 10-bit character stream encoded 10-bit character stream [8] pre-encoded 12-bit character stream rxsc/d rxsc/d rxsc/d rxdata[0] rxdata[0] rxd[0] [6, 9] rxdata[0] rxd[0] [6, 10] rxdata[1] rxdata[1] rxd[1] rxdata[1] rxd[1] rxdata[2] rxdata[2] rxd[2] rxdata[2] rxd[2] rxdata[3] rxdata[3] rxd[3] rxdata[3] rxd[3] rxdata[4] rxdata[4] rxd[4] rxdata[4] rxd[4] rxdata[5] rxdata[5] rxd[5] rxdata[5] rxd[5] rxdata[6] rxdata[6] rxd[6] rxdata[6] rxd[6] rxdata[7] rxdata[7] rxd[7] rxdata[7] rxd[7] rxdata[8]/rxcmd[3] rxcmd[3] rxd[8] rxdata[8] rxd[8] rxdata[9]/rxcmd[2] rxcmd[2] rxd[9] rxdata[9] [8] rxd[9] rxcmd[1] rxcmd[1] rxcmd[1] rxd[10] [10] rxcmd[0] rxcmd[0] rxcmd[0] rxd[11] vltn vltn vltn notes: 6. first bit shifted into the receiver. 7. when byte8/10 is high, received bit order is decoded form the serial stream and presented (msb to lsb) at rxdata[7,6,5,4] and rxdata[3,2,1,0] or rxcmd[3,2,1,0] as indicated by rxsc/d 8. when byte8/10 is low, received bit order is decoded form the serial stream and presented (msb to lsb) at rxdata[8,7,6,5,4] an d rxdata[9,3,2,1,0] or rxcmd[1,0] as indicated by rxsc/d 9. when encbyp is low and byte8/10 is high, the received bit order is (lsb to msb) rxd[0,1,2,3,4,5,6,7,8,9]. 10. when encbyp is low and byte8/10 is low, the received bit order is (lsb to msb) rxd[0,1,2,3,4,5,6,7,8,9,11,10].
preliminary CY7C9689 15 with existing control logic or external fifos with minimal or no external glue logic. encoder data from the host interface or transmit fifo is next passed to an encoder block. the CY7C9689 contains both 4b/5b and 5b/6b encoders that are used to improve the serial transport characteristics of the data. for those systems that contain their own encoder or scrambler, this encoder may be bypassed. serializer/line driver the data from the encoder is passed to a serializer. this se- rializer operates at 10 or 12 times the character rate. with the internal fifos enabled, refclk can run at 1x, 2x, or 4x the character rate. with the fifos bypassed, refclk can oper- ate at 1x or 2x the character rate. the serialized data is output in nrzi format from two pecl-compatible differential line driv- ers configured to drive transmission lines or optical modules. receive data interface line receiver/deserializer/framer serial data is received at one of two pecl-compatible differ- ential line receivers. the data is passed to both a clock and data recovery phase locked loop (pll) and to a deserializ- er that converts nrzi serial data into nrz parallel characters. the framer adjusts the boundaries of these characters to match those of the original transmitted characters. decoder the parallel characters are passed through a pair of 5b/4b or 6b/5b decoders and returned to their original form. for sys- tems that make use of external decoding or descrambling, the decoder may be bypassed. receive data interface/receive data fifo data from the decoder is passed either to a synchronous re- ceive fifo or is passed directly to the output register. the output register can be configured for either 8-bit character or 10-bit character operation. when configured for an asynchronous buffered (fifoed) in- terface, the data is passed through a 256-character receive fifo that allows data to be read at any rate from dc to 50 mhz. when configured for synchronous operation (receive fifo is bypassed) data is clocked out of the receive output register at up to 20 mhz when configured for 8-bit characters, or 16.67 mhz when configured for 10-bit characters. the re- ceive interface is also configurable for fifo flags with either high or low status indication oscillator speed selection the cy7b9689 is designed to operate over a two-octave range of serial signaling rates, covering the 50- to 200-mbaud range. to cover this wide range, the plls are configured into various sub-regions using the spdsel and rangesel in- puts, and to a limited extent the byte8/10 input. these inputs are used to configure the various prescalers and clock dividers used with the transmit and receive plls. maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with (power applied) ? 55 c to +125 c supply voltage to ground potential................ ? 0.5v to +6.5v dc voltage applied to outputs................ ? 0.5v to v dd +0.5v output current into ttl outputs (low) ..................... 30 ma dc input voltage ..................................... ? 0.5v to v dd +0.5v static discharge voltage ................................................> 2001v (per mil-std-883, method 3015) latch-up current ...........................................................> 200 ma operating range range ambient temperature v dd commercial 0 c to +70 c 5.0v 10% industrial ? 40 c to +85 c 5.0v 10%
preliminary CY7C9689 16 CY7C9689 dc electrical characteristics over the operating range parameter description test conditions min. max. unit ttl outputs v oht output high voltage i oh = ? 2 ma, v dd = min 2.4 v v olt output low voltage i ol = 8 ma, v dd = min 0.4 v i ost output short circuit current v out = 0v [11] ? 30 ? 80 ma ttl inputs v iht input high voltage 2.0 v v ilt input low voltage 0.8 v i iht input high current v in = v dd + 40 a i ilt input low current v in = 0.0v + 40 a i ilput input low current with internal pull-up v in = 0.0v ? 500 a transmitter pecl-compatible output pins: outa+, outa ? , outb+, outb ? v ohe output high voltage (v dd referenced) load = 50 ? to v dd ? 1.33v r curset =tbd v dd ? 1.03 v dd ? 0.83 v v ole output low voltage (v dd referenced) load = 50 ? to v dd ? 1.33v r curset =tbd v dd ? 2.0 v dd ? 1.62 v v odif output differential voltage |(out+) ? (out ? )| load = 50 ohms to v dd ? 1.33v r curset =tbdmin ? tbdmax 600 1100 mv receiver single-ended pecl-compatible input pin: cardet v ihe input high voltage (v dd referenced) v dd ? 1.165 v dd v v ile input low voltage (v dd referenced) 2.5 v dd ? 1.475 v receiver differential line receiver input pins: ina+, ina ? , inb+, inb ? v diff input differential voltage |(in+) ? (in ? )| 200 2500 mv v ihh highest input high voltage v dd v v ill lowest input low voltage 2.5 v i ihh input high current v in = v ihh max. 750 a i ill [12] input low current v in = v ill min. ? 200 a miscellaneous typ. max. i dd [13] power supply current freq. = max. commercial tbd 250 ma capacitance [14] parameter description test conditions max. unit c inttl ttl input capacitance t a = 25 c, f 0 = 1 mhz, v dd = 5.0v 7 pf c inpecl pecl input capacitance t a = 25 c, f 0 = 1 mhz, v dd = 5.0v 4 pf notes: 11. tested one output at a time, output shorted for less than one second, less than 10% duty cycle. 12. to guarantee positive currents for all pecl voltages, an external pull-down resistor must be present. 13. maximum i cc is measured with v dd = max, rfen = low, and outputs unloaded. typical i dd is measured with v dd = 5.0v, t a = 25 c, rfen = low, and outputs unloaded. 14. tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
preliminary CY7C9689 17 ac test loads and waveforms 2.0v 0.8v 3.0v 0.0v 2.0v 0.8v 5.0v output (a) ttl ac test load (b) pecl ac test load <1ns <1 ns 80% 20% 80% 20% (c) ttl input test waveform (d) pecl input test waveform r1 r2 c l c l r l r1=500 ? r2=333 ? (includes fixture and probe capacitance) r l =50 ? c l <5pf (includes fixture and probe capacitance) v ihe 3.0v v dd - 1.3 v ihe v ile v ile [15] [15] v th =1.5v v th =1.5v 250 ps 250 ps c l 10 pf CY7C9689 transmitter ttl switching characteristics, fifo enabled over the operating range parameter description min. max unit f ts txclk clock cycle frequency with transmit fifo enabled 50 mhz t txclk txclk period 20 ns t txcpwh txclk high time 6.5 ns t txcpwl txclk low time 6.5 ns t txclkr txclk rise time 0.7 5 ns t txclkf txclk fall time 0.7 5 ns t txa flag access time from txclk to output 4 15 ns t txds transmit data set-up time to txclk 4ns t txdh transmit data hold time from txclk 1ns t txens transmit enable set-up time to txclk 4ns t txenh transmit enable hold time from txclk 1ns t txrss transmit fifo reset (txrst ) set-up time to txclk 4ns t txrsh transmit fifo reset (txrst hold time from txclk 1ns t txces transmit chip enable (ce ) set-up time to txclk 4ns t txceh transmit chip enable (ce ) hold time from txclk 1ns t txza sample of ce low by txclk , output high-z to active high or low 0 ns t txoe sample of ce low by txclk to output valid 2 20 ns t txaz sample of ce high by txclk to output in high-z 2 20 ns note: 15. cypress uses constant current (ate) load configurations and forcing functions. this figure is for reference only.
preliminary CY7C9689 18 CY7C9689 receiver ttl switching characteristics, fifo enabled over the operating range parameter description min. max unit f ris rxclk clock cycle frequency with receive fifo enabled 50 mhz t rxclkip rxclk input period 20 ns t rxcpwh rxclk input high time 6.5 ns t rxcpwl rxclk input low time 6.5 ns t rxclkir rxclk input rise time 0.7 5 ns t rxclkif rxclk input fall time 0.7 5 ns t rxens receive enable set-up time to rxclk 4ns t rxenh receive enable hold time from rxclk 1ns t rxrss receive fifo reset (rxrxt ) set-up time to rxclk 4ns t rxrsh receive fifo reset (rxrxt ) hold time from rxclk 1ns t rxces receive chip enable (ce ) set-up time to rxclk 4ns t rxceh receive chip enable (ce ) hold time from rxclk 1ns t rxa flag and data access time from rxclk to output 4 15 ns t rxza sample of ce low by rxclk , output high-z to active high or low, [16] or sample of rxen asserted by rxclk , output high-z to active high or low 0ns t rxoe sample of ce low by rxclk to output valid, [16] or sample of rxen asserted by rxclk to rxdata outputs valid 220ns t rxza sample of ce high by rxclk to output in high-z, [16] or sample of rxen asserted by rxclk to rxdata outputs in high-z 220ns note: 16. parallel data output specifications are only valid if all outputs are loaded with similar dc and ac loads. CY7C9689 transmitter ttl switching characteristics, fifo bypassed over the operating range parameter description min. max unit t tra flag access time from refclk to output 4 15 ns t refds write data set-up time to refclk 4 ns t refdh write data hold time from refclk 1 ns t refens transmit enable set-up time to refclk 4 ns t refenh transmit enable hold time from refclk 1 ns t refces transmit chip enable (ce ) set-up time to refclk 4 ns t refceh transmit chip enable (ce ) hold time from refclk 1 ns t refza sample of ce low by refclk , output high-z to active high or low 0 ns t refoe sample of ce low by refclk to flag output valid 2 20 ns t refaz sample of ce high by refclk to flag output high-z 2 20 ns
preliminary CY7C9689 19 CY7C9689 receiver ttl switching characteristics, fifo bypassed over the operating range parameter description min. max unit f ros [17] rxclk clock output frequency ? 100 to 200 mbaud 8-bit operation (spdsel is high and byte8/10 is high) 10 20 mhz rxclk clock output frequency ? 50 to 100 mbaud 8-bit operation (spdsel is low and byte8/10 is high) 510mhz rxclk clock output frequency ? 100 to 200 mbaud 10-bit operation (spdsel is high and byte8/10 is low) 8.33 16.67 mhz rxclk clock output frequency ? 50 to 100 mbaud 10-bit operation (spdsel is low and byte8/10 is low) 4.16 8.33 mhz t rxclkop rxclk output period 25 240 ns t rxclkod rxclk output duty cycle 40 60 % t rxclkor rxclk output rise time 0.5 2 ns t rxclkof rxclk output fall time 0.5 2 ns t rxens receive enable set-up time to rxclk 4ns t rxenh receive enable hold time from rxclk 1ns t rxza sample of ce low by rxclk , outputs high-z to active sample of rxen asserted by rxclk to rxdata outputs high-z to active 0ns t rxoe sample of ce low by rxclk to flag output valid sample of rxen asserted by rxclk to rxdata output low-z 220ns t rxaz sample of ce high by rxclk to flag output high-z sample of rxen deasserted by rxclk to rxdata output high-z 220ns notes: 17. the period of t ros will match the period of the transmitter pll reference (refclk) w hen receiving serial data. when data is interrupted, rxclk may drift to refclk + 0.2%.
preliminary CY7C9689 20 CY7C9689 refclk input switching characteristics over the operating range parameter description conditions min. max unit spd- sel range- sel byte8/ 10 f ref refclk clock frequency ? 50 to 100 mbaud, 10-bit mode, refclk = 2x character rate 0 0 0 8.33 16.67 mhz refclk clock frequency ? 50 to 100 mbaud, 8-bit mode, refclk = 2x character rate 0 0 1 10 20 mhz refclk clock frequency ? 50 to 100 mbaud, 10-bit mode, refclk = 4x character rate 01 [18] 0 16.67 33.3 mhz refclk clock frequency ? 50 to 100 mbaud, 8-bit mode, refclk = 4x character rate 01 [18] 12040mhz refclk clock frequency ? 100 to 200 mbaud, 10-bit mode, refclk = character rate 1 0 0 20 40 mhz refclk clock frequency ? 100 to 200 mbaud, 8-bit mode, refclk = character rate 1 0 1 10 20 mhz refclk clock frequency ? 100 to 200 mbaud, 10-bit mode, refclk = 2x character rate 1 1 0 16.67 33.3 mhz refclk clock frequency ? 100 to 200 mbaud, 8-bit mode, refclk = 2x character rate 1 1 1 8.33 16.67 mhz t refclk refclk period 25 120 ns t refh refclk high time 6.5 ns t refl refclk low time 6.5 ns t refrx refclk frequency referenced to received clock period [19] ? 0.04 +0.04 % CY7C9689 pecl input/output switching characteristics over the operating range parameter description min. max unit t b bit time 20.0 5.0 ns t sa static alignment [14, 23] tbd tbd ps t efw error free window [14, 20, 24] 0.75 ui t rise pecl output rise time 20 ? 80% (pecl test load) [14] 200 1700 ps t fa ll pecl output fall time 80 ? 20% (pecl test load) [14] 200 1700 ps t dj deterministic jitter (peak-peak) [14, 25] tbd ps t rj random jitter ( ) [14, 26] tbd ps t jt transmitter total output jitter (peak-peak) [14] tbd ps notes: 18. when configured for synchronous operation with the fifos bypassed (fifobyp is low), if rangesel is high the spdsel input is ignored and operation is forced to the 100 ? 200 mbaud range 19. refclk has no phase or frequency relationship with rxclk and only acts as a centering reference to reduce clock synchronizat ion time. refclk must be within 0.04% of the transmitter pll reference (refclk) frequency, necessitating a 200-ppm crystal. 20. receiver ui (unit interval) is calculated as (1/f ref ) if no data is being received, or (1/f ref ) of the remote transmitter if data is being received. in an operating link this is equivalent to 10 * t b . 21. parallel data output specifications are only valid if all outputs are loaded with similar dc and ac loads. 22. the pecl switching threshold is the midpoint between the pecl ? v oh , and v ol specification (approximately v dd ? 1.33v). 23. static alignment is a measure of the alignment of the receiver sampling point to the center of a bit. static alignment is me asured by sliding one bit edge in 3,000 nominal transitions until a character error occurs. 24. error free window is a measure of the time window between bit centers where a transition may occur without causing a bit sam pling error. efw is measured over the operating range, input jitter < 50% dj. 25. while sending continuous jk, outputs loaded to 50 ? to v dd ? 1.3v, over the operating range. 26. while sending continuous hh, after 100,000 samples measured at the cross point of differential outputs, time referenced to r efclk input, over the operating range.
preliminary CY7C9689 21 CY7C9689 hotlink transmitter switching waveforms notes: 27. when extfifo is high, the write data is captured on the clock cycle following txen = high. 28. when extfifo is low, the write data is captured on the same clock cycle as the txen =low. no operation t txa t txa txclk t txclk t txcpwh t txcpwl txdata[7:0] txcmd[1:0] txen txfull txhalf txempty t txds t txdh t txens t txenh note 27 txdata[9:8]/txcmd[2:3] txsc/d txhalt asynchronous (fifo) interface fifobyp =high extfifo=high write cycle no operation t txa txclk txen txfull txhalf txempty t txdh t txds t txens t txenh note 28 t txa txdata[7:0] txcmd[1:0] txdata[9:8]/txcmd[2:3] txsc/d txhalt asynchronous (fifo) interface fifobyp =high extfifo=low write cycle
preliminary CY7C9689 22 note: 29. illustrates timing only. txen and txrst not usually active in same time period. CY7C9689 hotlink transmitter switching waveforms (continued) txclk txfull txhalf txempty t txoza t txoe t txoaz t txrss txrst t txrsh txdata[7:0] txcmd[1:0] txdata[9:8]/txcmd[2:3] txsc/d txhalt no operation txen asynchronous (fifo) interface fifobyp =high extfifo=high output enable timing ce t txceh t txces note 29 txclk txfull txhalf txempty ce t txoza t txoe t txoaz txrst t txrsh txdata[7:0] txcmd[1:0] xdata[9:8]/txcmd[2:3] txsc/d txhalt no operation txen asynchronous (fifo) interface fifobyp =high extfifo=low output enable timing ce t txces txrst t txceh note 29 t txrss
preliminary CY7C9689 23 notes: 30. when transferring data to the transmitter input from a depth expanded external fifo, the data is captured from the external fifo one clock cycle following the actual enable (txen = high). 31. when transferring data to the transmitter input from a synchronous external controller, the data is captured in the same clo ck cycle as the actual enable (txen = low). CY7C9689 hotlink transmitter switching waveforms (continued) no operation t tra t tra refclk txen txfull txhalf txempty t refds t refdh t refens t refenh note 30 txdata[7:0] txcmd[1:0] txdata[9:8]/txcmd[2:3] txsc/d txhalt synchronous interface fifobyp =low extfifo=high write cycle t refclk t refh t refl no operation refclk txen txfull txhalf txempty t refdh t refds t refens t refenh note 31 txdata[7:0] txcmd[1:0] data[9:8]/txcmd[2:3] txsc/d txhalt synchronous interface fifobyp =low extfifo=low write cycle
preliminary CY7C9689 24 CY7C9689 hotlink transmitter switching waveforms (continued) txfull txempty ce t refza t refoe t refaz t refces t refceh no operation refclk txdata[7:0] txcmd[1:0] txen t refens t refenh txdata[9:8]/txcmd[2:3] txsc/d txhalt synchronous interface fifobyp =low extfifo=high output enable timing no operation refclk txen txfull txempty ce txdata[7:0] txcmd[1:0] txdata[9:8]/txcmd[2:3] txsc/d txhalt synchronous interface fifobyp =low extfifo=low output enable timing
preliminary CY7C9689 25 CY7C9689 hotlink receiver switching waveforms notes: 32. when transferring data from the receive fifo to a depth expanded external fifo, the data is sent to the external fifo on the same clock cycle that rxen=high. rxempty=low indicates that data is available. 33. on inhibited reads, or if the receive fifo goes empty, the data outputs do not change. 34. when reading data from synchronous data interface, the data is captured on any clock cycle that rxen =low. rxempty =high indicates data is available. rxempty =low indicates that the fifo is empty. asynchronous (fifo) interface fifobyp =high no operation rxclk rxempty rxen valid data t rxclkip t rxcpwh t rxcpwl t rxens t rxenh ce t rxa read read t rxa note 32 note 33 fifo empty t rxclkop t rxclkod t rxclkod rxdata[9:8/rxcmd[2:3] rxcmd[1:0] rxdata[7:0] lfi rxfull rxhalf extfifo=high read cycle rxclk rxempty rxen valid data t rxenh ce t rxa read t rxa note 34 fifo empty t rxens asynchronous (fifo) interface fifobyp =high extfifo=low read cycle rxdata[9:8/rxcmd[2:3] rxcmd[1:0] rxdata[7:0] lfi rxfull rxhalf
preliminary CY7C9689 26 notes: 35. illustrates timing only. rxen and rxrst not usually active in same time period. 36. receive fifo reads are inhibited while the outputs are high-z. CY7C9689 hotlink receiver switching waveforms (continued) output enable timing no operation rxclk rxen t rxens t rxenh t rxza t rxoe t rxaz old data note 36 t rxrsh rxdata[9:8/rxcmd[2:3] rxcmd[1:0] rxdata[7:0] lfi rxfull rxrst t rxrss ce t rxces t rxceh note 35 refclk t refl t refh t refclk ina inb t b /2 ? t sa t b /2 ? t sa static alignment sample window ina inb t b t efw bit center bit center error-free window
preliminary CY7C9689 27 table 3. hotlink taxi compatible encoder patterns 4b/5b encoder 5b/6b encoder hex data 4-bit binary data [37] 5-bit encoded symbol [38,39] hex data 5-bit binary data [37] 6-bit encoded symbol [38,39] 0 0000 11110 00 00000 110110 1 0001 01001 01 00001 010001 2 0010 10100 02 00010 100100 3 0011 10101 03 00011 100101 4 0100 01010 04 00100 010010 5 0101 01011 05 00101 010011 6 0110 01110 06 00110 010110 7 0111 01111 07 00111 010111 8 1000 10010 08 01000 100010 9 1001 10011 09 01001 110001 a 1010 10110 0a 01010 110111 b 1011 10111 0b 01011 100111 c 1100 11010 0c 01100 110010 d 1101 11011 0d 01101 110011 e 1110 11100 0e 01110 110100 f 1111 11101 0f 01111 110101 10 10000 111110 11 10001 011001 12 10010 101001 13 10011 101101 14 10100 011010 15 10101 011011 16 10110 011110 17 10111 011111 18 10001 101010 19 11001 101011 1a 11010 101110 1b 11011 101111 1c 11100 111010 1d 11101 111011 1e 11110 111100 1f 11111 111101 notes: 37. binary input data is the parallel input data which is input to the transmitter and output from the receiver. binary bits are listed from left to right in the following order: 8-bit mode (byte8/10 is high and txsc/d or rxsc/d is low) ? txdata/rxdata[7], [6], [5], [4], and txdata/rxdata[3], [2], [1], [0]. 10-bit mode (byte8/10 is low and txsc/d or rxsc/d is low) ? txdata/rxdata[8], [7], [6], [5], [4], and txdata/rxdata[9], [3], [2], [1], [0]. 38. the encoded symbols are shown here as ? ones and zeros ? , but are converted to and from an nrzi stream at the transmitter output and receiver input. nrzi represents a ? one ? as a state transition (either low-to-high or high-to-low) and a ? zero ? as no transition within the bit interval. 39. encoded serial symbol bits are shifted out with the most significant bit (left-most) of the most significant nibble coming o ut first.
preliminary CY7C9689 28 functional description transmit fifo reset sequence on power-up, the transmitter and receiver fifos may contain random data. the transmitter fifo will empty automatically as the transmitter sends the random data (assuming that txhalt is not low) within the first 256 character-times after power is applied. the receiver fifo will retain any random data stored in it at power-up, and will accumulate all the ran- dom data being received from any attached transmitter as it is powered up. this random received data can be ? flushed ? by reading it, or the receive fifo can be ? reset ? to remove the unwanted data. the transmit fifo reset sequence (see figure 2 ) is started when txrst and ce are first sampled low by the rising edge of txclk. because a tx_rstmatch condition is present, the transmit fifo flags are asserted and can be used to track the status of any transmit fifo reset in progress. once the reset sequence has reached its maximum count (seven txclk cy- cles), the transmit fifo flags are asserted to indicate a full condition (txempty is deasserted, and both txhalf and txfull are asserted). this indicates that the transmit fifo reset has been recognized by the transmit control state ma- chine and that a reset has been started. however, if the txen is asserted prior to or during the assertion and sampling of txrst , the reset sequence is inhibited until txen is removed. note: the fifo full state forced by the reset operation is different from a full state caused by normal fifo data writes. for normal fifo write operations, when full is first asserted, the transmit fifo must still accept up to four addi- tional writes of data. when a full state is asserted due to a transmit fifo reset operation, the fifo will not accept any additional data. the transmit fifo reset does not complete until the external reset condition is removed. this can be removed by deasser- tion of either txrst or ce . if ce is deasserted (high) to table 4. hotlink taxi compatible command symbols CY7C9689 (transmitter) CY7C9689 (receiver) command input txcmd[3:0] command output rxcmd[3:0] hex binary cmd [40] encoded symbol [38, 39] mnemonic hex binary cmd [40] 8-bit mode (byte8/10 is high) 0 0000 11000 10001 jk (8-bit sync) 0 0000 1 0001 11111 11111 ii 1 0001 2 0010 01101 01101 tt 2 0010 3 0011 01101 11001 ts 3 0011 4 0100 11111 00100 ih 4 0100 5 0101 01101 00111 tr 5 0101 6 0110 11001 00111 sr 6 0110 7 0111 11001 11001 ss 7 0111 8 [41] 1000 00100 00100 hh 8 1000 9 [41] 1001 00100 11111 hi 9 1001 a [41] 1010 00100 00000 hq a 1010 b 1011 00111 00111 rr b 1011 c 1100 00111 11001 rs c 1100 d [41] 1101 00000 00100 qh d 1101 e [41] 1110 00000 11111 qi e 1110 f [41] 1111 00000 00000 qq f 1111 10-bit mode (byte8/10 is low) 0 00 011000 100011 lm (10-bit sync) 0 00 1 01 111111 111111 i ? i ? 101 2 10 011101 011101 t ? t ? 210 3 11 011101 111001 t ? s ? 311 notes: 40. binary cmd is the parallel input data which is input to the transmitter and output from the receiver. binary bits are listed from left to right in the following order: 8-bit mode (byte8/10 is high and txsc/d or rxsc/d is high) ? txcmd/rxcmd[3], [2], [1], [0]. 10-bit mode (byte8/10 is low and txsc/d or rxsc/d is high) ? txcmd/rxcmd[1], [0]. 41. while these commands are legal data and will not disrupt normal operation if used occasionally, they may cause data errors i f grouped into recurrent fields. normal pll operation cannot be guaranteed if one or more of these commands is continuously repeated.
preliminary CY7C9689 29 remove the reset condition, the transmit fifo flag ? s drivers are disabled, and the transmit fifo must be addressed at a later time to validate completion of the transmit fifo reset. if txrst is deasserted (high) to remove the reset condition, the tx_rstmatch is changed to a tx_match, and the transmit fifo status flags remain driven. the transmit fifo reset op- eration is complete when the transmit fifo flags indicate an empty state (txempty is asserted and both txhalf and txfull are deasserted). a valid transmit fifo reset se- quence is shown in figure 2 . here the txrst and ce are asserted (low) at the same time. when these signals are both sampled low by txclk, a tx_rstmatch condition is present. with txen deasserted (high), the transmit fifo is not selected for data transfers. this tx_rstmatch condition must remain for seven txclk cy- cles to initiate the tx_fifo_reset. following this the txfull fifo status flag is asserted to indicate that the transmit fifo reset sequence has completed and that a transmit fifo reset is in progress. when the txrst signal is deasserted (high), ce remains low to allow the fifo status flags to be driven. this allows the completion of the reset operation to be monitored. to allow better multi-tasking on multi-phy implementations, it is possi- ble to deassert ce (high) as soon as the full state is indi- cated. the fifo reset operation will complete and the empty state (indicating completion of the reset operation) can be de- tected during a separate polling operation. for those links implemented with a single phy, it is possible to hardwire ce low and still perform normal accesses and reset operations. this is shown in figure 3 . in a single-phy imple- mentation, a transmit fifo reset can never be initiated with txen asserted at the same time as txrst . since ce is always low, any assertion of txen causes the transmit fifo to be selected, clearing the reset counter. figure 4 shows a sequence of input signals which will not pro- duce a fifo reset. in this case txen was asserted to select a transmit fifo for data transfers. because txen remains active, the assertion of ce and txrst does not initiate a reset operation. this is shown by the txfull flag remaining high (deasserted) following what would be the normal expiration of the seven-state reset counter. receive fifo reset sequence the receive fifo reset sequence operates (for the most part) the same as the transmit fifo reset sequence. the same requirements exist for the assertion state of rxrst and se- lection of the interface. a sample receive fifo reset se- quence is shown in figure 5 . upon recognition of a receive fifo reset, the receive fifo flags are forced to indicate an empty state to prohibit additional reads from the fifo. unlike the transmit fifo, where the internal completion of the reset operation is shown by first going full and later going empty when the internal reset is complete, there is no secondary in- dication of the completion of the internal reset of the receive fifo. the receive fifo is usable as soon as new data is placed into it by the receive control state machine. notes: 42. signals shown as dotted lines indicate timing and levels when configured for external fifos (extfifo is high). 43. signal names listed in italics are internal signals, shown for reference only. figure 2. transmit fifo reset sequence txclk txrst tx_rstmatch tx_fifo_reset txfull txen ce tx_match not full full note 42 [43] [43] [43] note 42
preliminary CY7C9689 30 figure 3. transmit fifo reset sequence with constant ce txclk txrst tx_rstmatch tx_fifo_reset txfull txen ce tx_match [43] [43] [43] note 42 note 42 not full full figure 4. invalid transmit fifo reset sequence with txen asserted txclk txrst tx_rstmatch tx_fifo_reset txfull txen ce tx_match [43] [43] [43] note 42 note 42 not full
preliminary CY7C9689 31 figure 5. receive fifo reset sequence rxclk rxrst rx_rstmatch rx_fifo_reset rxempty rxen ce rx_match [43] [43] [43] note 42 note 42 not empty empty
preliminary CY7C9689 32 printed circuit board layout suggestions this is a typical printed circuit board layout showing example placement of power supply bypass components and other components mounted on the same side as the CY7C9689. other layouts, including cases with components mounted on the reverse side would work as well. CY7C9689-ac outa+ outb+ inb+ ina+ refclk curseta resistor cursetb resistor rxsc/d reset 0.01- f mlc x7r 1206 chip cap (2 sites) power supply bypass 0.01- f mlc x7r 1206 chip cap (4 sites) power supply bypass 0.01- f mlc x7r power supply bypass 0.01- f mlc x7r power supply bypass 0.01- f mlc x7r power supply bypass via to v dd plane via to v ss plane CY7C9689-ac
CY7C9689 preliminary ?cypress semiconductor corporation, 1999. the information contained herein is subject to change without notice. cypress semicon ductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. hotlink is a trademark of cypress semiconductor, inc. amd, taxi, and taxichip are trademarks of advanced micro devices. inc. ordering information ordering code package name package type operating range CY7C9689-ac a100 100-lead thin quad flat pack commercial CY7C9689-ai a100 100-lead thin quad flat pack industrial package diagram 100-pin thin plastic quad flat pack (tqfp) a100 51-85048-a

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